Phase Interpolator Based Clock and Data Recovery with Jitter Optimization

In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology applied for optimized design an 8-bit dual-loop CDR, designed with CMOS TSMC 65 nm process node. CDR extended, in terms resolution, version, novel PI topology work. loop has minimum frequency offset tracking ability equal to 500ppm at 5.83 Gbps, so suitable adoption either mesochronous or plesiochronous High Speed Serial Interface (HSSI) receivers. It consumes 14.2 mW 1 V supply voltage able achieve better than 10-10 Bit Error Rate (BER) performance. performance verification been realized through AMS simulator Analog Design Environment Cadence, by co-simulations transistor level Verilog-AMS generator.